I. Field of the Disclosure
The technology of the disclosure relates generally to shared cache memory systems, and, in particular, to controlling allocation of shared cache memory.
II. Background
An increasing number of computer hardware units (e.g. central processing units (CPUs), graphics processing units (GPUs), digital signal processing (DSP) units, and/or direct memory access (DMA) engines, as non-limiting examples) are configured to share memory system resources such as caches, memory, interconnect bandwidth, and cache bandwidth. Resource interference and conflicts between computer hardware units could result in negative consequences, such as missing a real-time deadline on a mobile System-on-Chip (SoC), or violating a Service Level Agreement (SLA) on a consolidated server, as non-limiting examples. Additionally, reference streams associated with some computer hardware units may have little temporal locality, leading to cache pollution and a negative impact on overall performance if left unchecked. In this regard, it may be desirable to enable users to control the usage of shared resources.
However, unlike most other performance-critical components of a system (e.g., CPU usage, memory usage, network bandwidth, and/or disk bandwidth), allocation of a conventional shared cache memory remains largely outside the control of users. As a result, such conventional shared cache memory systems may remain underutilized to protect against worst case performance in the presence of cache interference. Moreover, existing cache Quality of Service (QoS) and partitioning schemes may lack the flexibility necessary to address multiple use cases, such as strict capacity allocation and/or throughput maximization, as non-limiting examples.